1. Field of the Invention
This invention relates to a computer processing system for providing fault injection verification of soft error rate (SER) sensitive logic devices for a computer design, particularly to provide a rating of the logic devices for soft error resilience, and to an automated production of an integrated circuit design process for devices carried out by a computer, computer network or apparatus, particularly through a computer method for the execution of software for automated verification of soft error resilience of devices to be used in integrated circuits from logic design data for those integrated circuits.
2. Description of Background
Before our invention, the U.S. Pat. No. 7,065,726, entitled “System and method for guiding and optimizing formal verification for a circuit design”, incorporated fully herein by reference, suggested a formal verification guidance method for circuit design which involves modifying an analysis region manually if verification of the circuit design being verified results in determination that the analysis region is not verified. The abstract of U.S. Pat. No. 7,065,726 said that: “The present invention is used for guiding formal verification of a circuit design in circuit simulation software to optimize the time required for verification of a circuit design. The invention modifies the analysis region being used for verification in order to optimize the time for verification. The invention allows for manual, semi-automatic, and automatic modification of the analysis region. The modification is done by either expanding or reducing the analysis region or by adding new rules as assumptions to the existing analysis region. The invention also uses the concept of an articulation point for modification of the analysis region. The modification of the analysis region is performed in a manner to optimize time and memory required for verification of the circuit design.”
The improvement claimed in U.S. Pat. No. 7,065,726 was for a method for guiding formal verification for a circuit design in circuit simulation software to optimize the time required for verification of the circuit design, the method comprising the steps of:    a. identifying an analysis region for verifying the circuit design;    b. verifying the circuit design by applying formal verification over the analysis region;    c. manually modifying the analysis region if verification of the circuit design over the analysis region results in a determination that the analysis region is not verified including the steps of:    1. selecting a signal in the analysis region; and    2. adding a portion of the circuit design relating to the signal in the analysis region including adding an articulated fan-in driving the signal to the analysis region by identifying the articulated fan-in of the signal by traversing the circuit design backwards from the signal until a signal from the group consisting of primary inputs, storage elements and articulation points is encountered.An automated production of computer chips with a design process carried out by a computer, computer network or apparatus, particularly through a computer method for the execution of software for automated verification of soft error resilience of devices to be used in integrated circuits from logic design data for those integrated circuits.This patent illustrated a way to find state machines and FIFO (First In First Out) within general design data for purposes other than SER verification which tools can be used like those here described for state machine and FIFO. However the use of the tools in the suggested formal verification guidance method still involved modifying analysis regions manually.